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Version 2.0, 8 May 2006
CoolSETTM-F3
ICE3 B03 6 5 L ICE3 A10 6 5 L ICE3 A15 6 5 L
Off-Line SMPS Current Mode Controller with integrated 650V Startup Cell/Depletion CoolMOSTM and Latched off Mode
Power Management & Supply
Never
stop
thinking.
CoolSETTM-F3 ICE3xxx65L Revision History: Page 11, 12, 13 15 20
3, 23 25
2006-05-08
Datasheet
Previous Version: 1.0 ( ICE3A1065L/ICE3A1565L ), 1.2 ( ICE3B0365L ) Subjects (major changes since last revision)
Group ICE3B0365L, ICE3A1065L and ICE3A1565L together Revise typo to trigger level at FB ( C5 ) Revise pulse drain current Add temperature derating curve Add marking Add PCB layout recommendation
For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http:// www.infineon.com CoolMOSTM, CoolSETTM are trademarks of Infineon Technologies AG.
Edition 2006-05-08 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen
(c) Infineon Technologies AG 1999. All Rights Reserved.
Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
CoolSETTM-F3
ICE3xxx65L
Off-Line SMPS Current Mode Controller with integrated 650V Startup Cell/Depletion CoolMOSTM and Latched off Mode
Product Highlights
* Active Burst Mode to reach the lowest Standby Power Requirements < 100mW * Latched Off Mode and Auto Restart Mode to increase robustness and safety of the system * Adjustable Blanking Window for high load jumps to increase system reliability * Pb-free lead plating DIP package; RoHS compilant
PG-DIP-8-6 test
Features
* * * * * * * * * * * * * * * * 650V avalanche rugged CoolMOSTM with built in switchable Startup Cell Active Burst Mode for lowest Standby Power @ light load controlled by Feedback Signal Fast load jump response in Active Burst Mode 67/100kHz internally fixed switching frequency Latched Off Mode for Overtemperature Detection Latched Off Mode for Overvoltage Detection Latched Off Mode for Short Winding Detection Auto Restart Mode for Overload and Open Loop Auto Restart Mode for VCC Undervoltage Blanking Window for short duration high current User defined Soft Start Minimum of external components required Max Duty Cycle 72% Overall tolerance of Current Limiting < 5% Internal PWM Leading Edge Blanking Soft driving for low EMI
Description
The new generation CoolSETTM-F3 Controller provides Active Burst Mode to reach the lowest Standby Power Requirements <100mW at no load. As the controller is always active during Active Burst Mode, there is an immediate response on load jumps without any black out in the SMPS. In Active Burst Mode the ripple of the output voltage can be reduced <1%. Furthermore, to increase the robustness and safety of the system, the device enters into Latched Off Mode in the cases of Overtemperature, Overvoltage or Short Winding. The Latched Off Mode can only be reset by disconnecting the main line. Auto Restart Mode is entered for cases like open loop or overload. By means of an internal precise peak current limitation, the dimension of the transformer and the secondary diode can be lowered which leads to more cost efficiency. An adjustable blanking window prevents the IC from entering Auto Restart Mode or Active Burst Mode unintentionally in case of high load jumps.
Typical Application
+
85 ... 270 VAC
CBulk CVCC
Snubber
Converter DC Output
-
VCC
Power Management PWM Controller Current Mode Precise Low Tolerance Peak Current Limitation Active Burst Mode Latched Off Mode Auto Restart Mode
Drain
Startup Cell
CoolMOSTM
CS RSense FB SoftS
GND
Control Unit
CoolSETTM-F3
with Latch off Mode
CSoftS
Type ICE3B0365L ICE3A1065L ICE3A1565L
1) 2)
Package PG-DIP-8-6 PG-DIP-8-6 PG-DIP-8-6
Marking ICE3B0365L ICE3A1065L ICE3A1565L
VDS 650V 650V 650V
FOSC 67KHz 100kHz 100KHz
RDSon1) 6.45 2.95 1.70
230VAC 15%2) 22W 32W 42W
85-265 VAC2) 10W 16W 20W
typ @ T=25C Calculated maximum input power rating at Ta=75C, Tj=125C and without copper area as heat sink.
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Table of Contents 1 1.1 1.2 2 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 3.5 3.5.1 3.5.2 3.6 3.6.1 3.6.2 3.6.2.1 3.6.2.2 3.6.2.3 3.6.3 3.6.3.1 3.6.3.2 4 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 5 6 7 8 Page
Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Configuration with PG-DIP-8-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Representative Blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Startup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 PWM-Latch FF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Leading Edge Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Propagation Delay Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Adjustable Blanking Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Entering Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Working in Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Leaving Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Latched Off Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Auto Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 CoolMOSTM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Temperature derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Schematic for recommended PCB layout . . . . . . . . . . . . . . . . . . . . . . . .25
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Pin Configuration and Functionality
1
1.1
Pin 1 2 3 4 5 6 7 8
1)
Pin Configuration and Functionality
Pin Configuration with PG-DIP-8-6
Symbol SoftS FB CS Drain Drain n.c. VCC GND at Tj = 110C Function Soft-Start Feedback Current Sense/ 650V1) Depl. CoolMOSTM Source 650V1) Depl. CoolMOSTM Drain 650V1) Depl. CoolMOSTM Drain Not Connected Controller Supply Voltage Controller Ground FB (Feedback) The information about the regulation is provided by the FB Pin to the internal Protection Unit and to the internal PWM-Comparator to control the duty cycle. The FBSignal controls in case of light load the Active Burst Mode of the controller. CS (Current Sense) The Current Sense pin senses the voltage developed on the series resistor inserted in the source of the integrated Depl. CoolMOSTM. If CS reaches the internal threshold of the Current Limit Comparator, the Driver output is immediately switched off. Furthermore the current information is provided for the PWMComparator to realize the Current Mode.
1.2
Pin Functionality
SoftS (Soft Start & Auto Restart Control) The SoftS pin combines the functions of Soft Start during Start Up and error detection for Auto Restart Mode. These functions are implemented and can be adjusted by means of an external capacitor at SoftS to ground. This capacitor also provides an adjustable blanking window for high load jumps, before the IC enters into Auto Restart Mode.
Package PG-DIP-8-6
SoftS
1
8
GND
Drain (Drain of integrated Depl. CoolMOSTM) Pin Drain is the connection to the Drain of the internal Depl. CoolMOSTM. VCC (Power supply) The VCC pin is the positive supply of the IC. The operating range is between 8.5V and 21V. GND (Ground) The GND pin is the ground of the controller.
FB
2
7
VCC
CS
3
6
n.c.
Drain
4
5
Drain
Figure 1 Note:
Pin Configuration PG-DIP-8-6(top view) Pin 4 and 5 are shorted within the DIP 8 package.
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2
Figure 2
+ CBulk Snubber Converter DC Outpu VOUT CVCC
Version 2.0
VCC
Power Management Internal Bias Voltage Reference 6.5V
85 ... 270 VAC
Drain
Startup Cell
6.5V
RSoftS
3.25k
SoftS
CoolMOSTM
T2
T3
1V Undervoltage Lockout
15V 0.72 8.5V
Latched Off Mode Reset VVCC < 6V
GND
T1 Oscillator
Duty Cycle max
Representative Blockdiagram
Power-Down Reset PWM Section 1 G3 Latched Off Mode Soft Start Soft-Start Comparator
Clock
CSoftS
5k
VCC
4.4V C7 Gate Driver & G9 & G7 1 G8 PWM Comparator C8 C11 Auto Restart Mode Propagation-Delay Compensation
0.85V
21V
C1
& G1
Spike Blanking 8.0us
Thermal Shutdown
Tj >140C
S1
4.0V
C2
Representative Blockdiagram
6
Spike Blanking 190ns 1.66V & G6 C10 x3.7 PWM OP C12 & G11 Current Mode & G10 Active Burst Mode 10k 1pF D1 Vcsth Leading Edge Blanking 220ns 0.257V Current Limiting
1
FF1 S RQ
G2
5.4V
C3
6.5V
RFB
4.8V
C4
&
G5
5k
FB
C5
CS
RSense
10pF
1.30V
4.0V
C6a
Control Unit
3.4V
C6b
ICE3xxxxxL / CoolSETTM-F3 with Latched off Mode
CoolSETTM-F3 ICE3xxx65L
Representative Blockdiagram
8 May 2006
CoolSETTM-F3 ICE3xxx65L
Functional Description
3
Functional Description
All values which are used in the functional description are typical values. For calculating the worst cases the min/max values which can be found in section 4 Electrical Characteristics have to be considered.
power limitation can be avoided together with the integrated Propagation Delay Compensation. Therefore the maximum power is nearly independent on the input voltage which is required for wide range SMPS. There is no need for an extra over-sizing of the SMPS, e.g. the transformer or the secondary diode.
3.1
Introduction
3.2
Drain
Power Management
VCC Startup Cell
CoolSETTM-F3 is the further development of the CoolSETTM-F2 to meet the requirements for the lowest Standby Power at minimum load and no load conditions. A new fully integrated Standby Power concept is implemented into the IC in order to keep the application design easy. Compared to CoolSETTM-F2 no further external parts are needed to achieve the lowest Standby Power. An intelligent Active Burst Mode is used for this Standby Mode. After entering this mode there is still a full control of the power conversion by the secondary side via the same optocoupler that is used for the normal PWM control. The response on load jumps is optimized. The voltage ripple on Vout is minimized. Vout is further on well controlled in this mode. The usually external connected RC-filter in the feedback line after the optocoupler is integrated in the IC to reduce the external part count. Furthermore a high voltage Startup Cell is integrated into the IC which is switched off once the Undervoltage Lockout on-threshold of 15V is exceeded. This Startup Cell is part of the integrated Depl. CoolMOSTM. The external startup resistor is no longer necessary as this Startup Cell is connected to the Drain. Power losses are therefore reduced. This increases the efficiency under light load conditions drastically. The Soft-Start capacitor is also used for providing an adjustable blanking window for high load jumps. During this time window the overload detection is disabled. With this concept no further external components are necessary to adjust the blanking window. In order to increase the robustness and safety of the system, the IC provides 2 levels of protection modes: Latched Off Mode and Auto Restart Mode. The Latched Off Mode is only entered under dangerous conditions which can damage the SMPS if not switched off immediately. A restart of the system can only be done by disconnecting the AC line. The Auto Restart Mode reduces the average power conversion to a minimum under unsafe operating conditions. This is necessary for a prolonged fault condition which could otherwise lead to a destruction of the SMPS over time. Once the malfunction is removed, normal operation is automatically initiated after the next Start Up Phase. The internal precise peak current limitation reduces the costs for the transformer and the secondary diode. The influence of the change in the input voltage on the
Depl. CoolMOSTM
Power Management Internal Bias Latched Off Mode Reset VVCC < 6V Power-Down Reset Undervoltage Lockout 15V 8.5V
Voltage Reference
6.5V
Auto Restart Mode Active Burst Mode Latched Off Mode
T1
SoftS
Figure 3 Power Management
The Undervoltage Lockout monitors the external supply voltage VVCC. When the SMPS is plugged to the main line the internal Startup Cell is biased and starts to charge the external capacitor CVCC which is connected to the VCC pin. This VCC charge current which is provided by the Startup Cell from the Drain pin is 1.05mA. When VVCC exceeds the on-threshold VCCon=15V the internal voltage reference and bias circuit are switched on. Then the Startup Cell is switched off by the Undervoltage Lockout and therefore no power losses present due to the connection of the Startup Cell to the Drain voltage. To avoid uncontrolled ringing at switch-on a hysteresis is implemented. The switch-off of the controller can only take place after Active Mode was entered and VVCC falls below 8.5V.
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CoolSETTM-F3 ICE3xxx65L
Functional Description
The maximum current consumption before the controller is activated is about 160A. When VVCC falls below the off-threshold VCCoff=8.5V the internal reference is switched off and the Power Down reset let T1 discharging the soft-start capacitor CSoftS at pin SoftS. Thus it is ensured that at every startup cycle the voltage ramp at pin SoftS starts at zero. The internal Voltage Reference is switched off if Latched Off Mode or Auto Restart Mode is entered. The current consumption is then reduced to 300A. Once the malfunction condition is removed, this block will then turn back on. The recovery from Auto Restart Mode does not require disconnecting the SMPS from the AC line. In case Latched Off Mode is entered, VCC needs to be lowered below 6V to reset the Latched Off Mode. This is done usually by disconnecting the SMPS from the AC line. When Active Burst Mode is entered the internal Bias is switched off in order to reduce the current consumption below 1.05mA while keeping the Voltage Reference still active as this is necessary in this mode. signal VSoftS which is generated by the external capacitor CSofts in combination with the internal pull up resistor RSoftS, determines the duty cycle until VSoftS exceeds 4V. When the Soft Start begins, CSoftS is immediately charged up to approx. 1V by T2. Therefore the Soft Start Phase takes place between 1V and 4V. Above VSoftsS = 4V there is no longer duty cycle limitation DCmax which is controlled by comparator C7 since comparator C2 blocks the gate G7 (see Figure 4). This maximum charge current in the very first stage when VSoftS is below 1V, is limited to 1.30mA.
VSoftS
max. Startup Phase 5.4V 4V
1V max. Soft Start Phase
3.3
Startup Phase
6.5V 3.25k
DCmax
DC1 DC2
t
RSoftS
T2 T3 1V
SoftS
CSoftS Soft Start C7 Soft-Start Comparator & G7 C2 4V
t1
Figure 5
Gate Driver
t2 t
Startup Phase
0.85V x3.7 PWM OP CS
By means of this extra charge stage, there is no delay in the beginning of the Startup Phase when there is still no switching. Furthermore Soft Start is finished at 4V to have faster the maximum power capability. The duty cycles DC1 and DC2 are depending on the mains and the primary inductance of the transformer. The limitation of the primary current by DC2 is related to VSoftS = 4V. But DC1 is related to a maximum primary current which is limited by the internal Current Limiting with CS = 1V. Therefore the maximum Startup Phase is divided into a Soft Start Phase until t1 and a phase from t1 until t2 where maximum power is provided if demanded by the FB signal.
Figure 4
Soft Start
At the beginning of the Startup Phase, the IC provides a Soft Start duration whereby it controls the maximum primary current by means of a duty cycle limitation. A
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CoolSETTM-F3 ICE3xxx65L
Functional Description 3.4 PWM Section
0.72 Oscillator Duty Cycle max
PWM-Latch
3.4.3
Gate Driver
PWM Section
VCC
Clock
1
Gate
Soft Start Comparator PWM Comparator Current Limiting
FF1 1 G8 S R Q Gate Driver & G9
Gate Driver
CoolMOSTM
Figure 7
Internal CoolMOSTM Gate
Gate Driver
Figure 6
PWM Section Block
The driver-stage is optimized to minimize EMI and to provide high circuit efficiency. This is done by reducing the switch on slope when exceeding the internal CoolMOSTM threshold. This is achieved by a slope control of the rising edge at the driver's output (see Figure 8).
3.4.1 Oscillator The oscillator generates a fixed frequency. The switching frequency for ICE3Axx65L is fOSC = 100kHz and ICE3Bxx65L is fOSC = 67kHz. A resistor, a capacitor and a current source and current sink which determine the frequency are integrated. The charging and discharging current of the implemented oscillator capacitor are internally trimmed, in order to achieve a very accurate switching frequency. The ratio of controlled charge to discharge current is adjusted to reach a maximum duty cycle limitation of Dmax=0.72. 3.4.2 PWM-Latch FF1 The oscillator clock output provides a set pulse to the PWM-Latch when initiating the internal CoolMOSTM conduction. After setting the PWM-Latch can be reset by the PWM comparator, the Soft Start comparator or the Current-Limit comparator. In case of resetting, the driver is shut down immediately.
(internal) VGate
ca. t = 130ns 5V
t
Figure 8 Gate Rising Slope Thus the leading switch on spike is minimized. When the integrated CoolMOSTM is switched off, the falling shape of the driver is slowed down when reaching 2V to prevent an overshoot below ground. Furthermore the driver circuit is designed to eliminate cross conduction of the output stage. During powerup when VCC is below the undervoltage lockout threshold VVCCoff, the output of the Gate Driver is low to disable power transfer to the secondary side.
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CoolSETTM-F3 ICE3xxx65L
Functional Description 3.5
PWM Latch FF1
Current Limiting
Latched Off Mode Current Limiting Spike Blanking 190ns Propagation-Delay Compensation Vcsth C10 PWM-OP & G10 C12 0.257V 1.66V C11
short winding in the transformer or the secondary diode is shorten. To ensure that there is no accidentally entering of the Latched Mode by the comparator C11 a spike blanking with 190ns is integrated in the output path of comparator C11. 3.5.1 Leading Edge Blanking
VSense
Vcsth tLEB = 220ns
Leading Edge Blanking 220ns
t
Figure 10 Leading Edge Blanking Each time when the internal CoolMOSTM is switched on, a leading edge spike is generated due to the primary-side capacitances and secondary-side rectifier reverse recovery time. This spike can cause the gate drive to switch off unintentionally. To avoid a premature termination of the switching pulse, this spike is blanked out with a time constant of tLEB = 220ns. During this time, the gate drive will not be switched off.
Active Burst Mode
10k D1
1pF
CS
Figure 9 Current Limiting Block
3.5.2
Propagation Delay Compensation
There is a cycle by cycle Current Limiting realized by the Current-Limit comparator C10 to provide an overcurrent detection. The source current of the internal CoolMOSTM is sensed via an external sense resistor RSense . By means of RSense the source current is transformed to a sense voltage VSense which is fed into the pin CS. If the voltage VSense exceeds the internal threshold voltage Vcsth the comparator C10 immediately turns off the gate drive by resetting the PWM Latch FF1. A Propagation Delay Compensation is added to support the immediate shut down without delay of the internal CoolMOSTM in case of Current Limiting. The influence of the AC input voltage on the maximum output power can thereby be avoided. To prevent the Current Limiting from distortions caused by leading edge spikes a Leading Edge Blanking is integrated in the current sense path for the comparators C10, C12 and the PWM-OP. The output of comparator C12 is activated by the Gate G10 if Active Burst Mode is entered. Once activated the current limiting is thereby reduced to 0.257V. This voltage level determines the power level when the Active Burst Mode is left if there is a higher power demand. A further comparator C11 is implemented to detect dangerous current levels which could occur if there is a
In case of overcurrent detection, the switch-off of the internal CoolMOSTM is delayed due to the propagation delay of the circuit. This delay causes an overshoot of the peak current Ipeak which depends on the ratio of dI/ dt of the peak current (see Figure 11).
Signal2 ISense Ipeak2 Ipeak1 ILimit IOvershoot2
Signal1 tPropagation Delay
IOvershoot1
t
Figure 11 Current Limiting The overshoot of Signal2 is bigger than of Signal1 due to the steeper rising waveform. This change in the slope is depending on the AC input voltage. Propagation Delay Compensation is integrated to limit the overshoot dependency on dI/dt of the rising primary
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CoolSETTM-F3 ICE3xxx65L
Functional Description
current. That means the propagation delay time between exceeding the current sense threshold Vcsth and the switch off of the internal CoolMOSTM is compensated over temperature within a wide range. Current Limiting is now possible in a very accurate way. E.g. Ipeak = 0.5A with RSense = 2. Without Propagation Delay Compensation the current sense threshold is set to a static voltage level Vcsth=1V. A current ramp of dI/dt = 0.4A/s, that means dVSense/dt = 0.8V/s, and a propagation delay time of i.e. tPropagation Delay =180ns leads then to an Ipeak overshoot of 14.4%. By means of propagation delay compensation the overshoot is only about 2% (see Figure 12).
with compensation without compensation
3.6
Control Unit
The Control Unit contains the functions for Active Burst Mode, Auto Restart Mode and Latched Off Mode. The Active Burst Mode and the Auto Restart Mode are combined with an Adjustable Blanking Window which is depending on the external Soft Start capacitor. By means of this Adjustable Blanking Window, the IC avoids entering into these two modes accidentally. Furthermore it also provides a certain time whereby the overload detection is delayed. This delay is useful for applications which normally works with a low current and occasionally require a short duration of high current. 3.6.1 Adjustable Blanking Window
V
1,3 1,25 1,2
SoftS
6.5V 5k R SoftS
VSense
1,15 1,1 1,05 1 0,95 0,9 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2
4.4V 1 & G4
dVSense dt
V s
S1
G2
Figure 12
Overcurrent Shutdown
5.4V 4.8V
The Propagation Delay Compensation is realized by means of a dynamic threshold voltage Vcsth (see Figure 13). In case of a steeper slope the switch off of the driver is earlier to compensate the delay.
C3
& C4 G5
Auto Restart Mode
VOSC
max. Duty Cycle
Active Burst Mode
off time
FB
& G6 C6
VSense Vcsth
Propagation Delay
t
1.30V Control Unit
Figure 14
Adjustable Blanking Window
Signal1
Figure 13
Signal2
t
Dynamic Voltage Threshold Vcsth
VSoftS is clamped at 4.4V by the closed switch S1 after the SMPS is settled. If overload occurs VFB is exceeding 4.8V. Auto Restart Mode can't be entered as the gate G5 is still blocked by the comparator C3. But after VFB has exceeded 4.8V the switch S1 is opened via the gate G2. The external Soft Start capacitor can now be charged further by the integrated pull up resistor RSoftS. The comparator C3 releases the gates G5 and G6 once VSofts has exceeded 5.4V. Therefore there is no entering of Auto Restart Mode possible during this charging time of the external capacitor
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CoolSETTM-F3 ICE3xxx65L
Functional Description
CSoftS. The same procedure happens to the external Soft Start capacitor if a low load condition is detected by comparator C5 when VFB is falling below 1.30V. Only after VSoftS has exceeded 5.4V and VFB is still below 1.30V Active Burst Mode is entered. 3.6.2 Active Burst Mode The controller provides Active Burst Mode for low load conditions at VOUT. Active Burst Mode increases significantly the efficiency at light load conditions while supporting a low ripple on VOUT and fast response on load jumps. During Active Burst Mode which is controlled only by the FB signal the IC is always active and can therefore immediately response on fast changes at the FB signal. The Startup Cell is kept switched off to avoid increased power losses for the self supply. 3.6.2.1 Entering Active Burst Mode The FB signal is always observed by the comparator C5 if the voltage level falls below 1.30V. In that case the switch S1 is released which allows the capacitor CSoftS to be charged starting from the clamped voltage level at 4.4V in normal operating mode. If VSoftS exceeds 5.4V the comparator C3 releases the gate G6 to enter the Active Burst Mode. The time window that is generated by combining the FB and SoftS signals with gate G6 avoids a sudden entering of the Active Burst Mode due to large load jumps. This time window can be adjusted by the external capacitor CSoftS. After entering Active Burst Mode a burst flag is set and the internal bias is switched off in order to reduce the current consumption of the IC down to approx. 1.05mA. In this Off State Phase the IC is no longer self supplied so that therefore CVCC has to provide the VCC current (see Figure 16). Furthermore gate G11 is then released to start the next burst cycle once VFB has 3.4V exceeded. It has to be ensured by the application that the VCC remains above the Undervoltage Lockout Level of 8.5V to avoid that the Startup Cell is accidentally switched on. Otherwise power losses are significantly increased. The minimum VCC level during Active Burst Mode is depending on the load conditions and the application. The lowest VCC level is reached at no load conditions at VOUT. 3.6.2.2 Working in Active Burst Mode After entering the Active Burst Mode the FB voltage rises as VOUT starts to decrease due to the inactive PWM section. Comparator C6a observes the FB signal if the voltage level 4V is exceeded. In that case the internal circuit is again activated by the internal Bias to start with switching. As now in Active Burst Mode the gate G10 is released the current limit is only 0.257V to reduce the conduction losses and to avoid audible noise. If the load at VOUT is still below the starting level for the Active Burst Mode the FB signal decreases down to 3.4V. At this level C6b deactivates again the internal circuit by switching off the internal Bias. The gate G11 is released as after entering Active Burst Mode the burst flag is set. If working in Active Burst Mode the FB voltage is changing like a saw tooth between 3.4V and 4V (see Figure 16). 3.6.2.3 Leaving Active Burst Mode The FB voltage immediately increases if there is a high load jump. This is observed by comparator C4. As the current limit is ca. 26% during Active Burst Mode a certain load jump is needed that FB can exceed 4.8V. At this time C4 resets the Active Burst Mode which also
SoftS
6.5V 5k 4.4V RSoftS Internal Bias
S1
Current Limiting & C3
5.4V 4.8V C4
G10
FB
1.30V
C5
& G6
Active Burst Mode
C6a 4.0V & C6b 3.4V Control Unit G11
Figure 15
Active Burst Mode
The Active Burst Mode is located in the Control Unit. Figure 15 shows the related components.
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Functional Description
blocks C12 by the gate G10. Maximum current can now be provided to stabilize VOUT. 3.6.3 Protection Modes The IC provides several protection features which are separated into two categories. Some enter Latched Off Mode, the others enter Auto Restart Mode. The Latched Off Mode can only be reset if VCC is falling below 6V. Both modes prevent the SMPS from destructive states. The following table shows the relationship between possible system failures and the chosen protection modes. VCC Overvoltage
t Blanking Window 5.40V 4.40V
VFB
4.80V 4.00V 3.40V 1.30V
Entering Active Burst Mode
Leaving Active Burst Mode
VSoftS
Latched Off Mode Latched Off Mode Auto Restart Mode Auto Restart Mode Auto Restart Mode Auto Restart Mode
Overtemperature Overload Open Loop VCC Undervoltage Short Optocoupler 3.6.3.1
Short Winding/Short Diode Latched Off Mode
VCS
Current limit level during 1.00V Active Burst Mode 0.257V
t
Latched Off Mode
CS
Latched Off Mode Reset VVCC < 6V Spike Blanking 190ns 1 G3 Latched Off Mode
VVCC
t
C11 1.70V
8.5V
IVCC
7.2mA
t
VCC C1 28V
Spike Blanking 8.0us
1.05mA
VOUT
Max. Ripple < 1%
Thermal Shutdown
t
Voltage Reference
Tj >140C Control Unit
Figure 17
t
Latched Off Mode
Figure 16
Signals in Active Burst Mode
The VCC voltage is observed by comparator C1 if 21V is exceeded. The output of C1 is combined with the output of C4 which observes FB signal if 4.8V is
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Functional Description
exceeded. Therefore the overvoltage detection is only activated if the FB signal is outside the operating range > 4.8V, e.g. when Open Loop happens. This means any small voltage overshoots of VVCC during normal operating can not start the Latched Off Mode. The internal Voltage Reference is switched off once Latched Off Mode is entered in order to reduce the current consumption of the IC as much as possible. Latched Off Mode can only be reset by decreasing VVCC < 6V. In this stage, only the UVLO is working which controls the Startup Cell by switching on/off at VVCCon/VVCCoff. During this phase, the average current consumption is only 300A. As there is no longer a selfsupply by the auxiliary winding, VCC drops. The Undervoltage Lockout switches on the integrated Startup Cell when VCC falls below 8.5V. The Startup Cell is switched off again when VCC has exceeded 15V. Once the Latched Off Mode was entered, there is no Start Up Phase after VCC has exceeded the switchon level of the Undervoltage Lockout. Therefore VCC changes between the switch-on and switch-off levels of the Undervoltage Lockout with a saw tooth shape (see Figure 18). operating mode comparator C10 keeps the maximum level of the CS signal at 1V. If there is a failure such as short winding or short diode, C10 is no longer able to limit the CS signal at 1V. C11 detects then the over current and enters immediately the Latched Off Mode to keep the SMPS in a safe stage. 3.6.3.2 Auto Restart Mode
SoftS
6.5V 5k RSoftS
4.4V 1 S1 G2 Voltage Reference C3 5.4V 4.8V C4 & G5 Auto Restart Mode Control Unit
VVCC
t.b.d
8.5V
FB
t
IVCCStart
1.05mA
Figure 19
Auto Restart Mode
VOUT
Figure 18 Signals in Latched Off Mode
t
The Thermal Shutdown block monitors the junction temperature of the IC. After detecting a junction temperature higher than 140C, Latched Off Mode is entered. The signals coming from the temperature detection and VCC overvoltage detection are fed into a spike blanking with a time constant of 8.0s to ensure system reliability. Furthermore, a short winding or short diode on the secondary side can be detected by the comparator C11 which is in parallel to the propagation delay compensated current limit comparator C10. In normal
In case of Overload or Open Loop, FB exceeds 4.8V which will be observed by C4. At this time S1 is released that VSoftS can increase. If VSoftS exceeds 5.4V which is observed by C3, Auto Restart Mode is entered as both inputs of the gate G5 are high. In combining the FB and SoftS signals, there is a blanking window generated which prevents the system to enter Auto Restart Mode due to large load jumps. This time window is the same as for the Active Burst Mode and can therefore be adjusted by the external CSoftS. In case of VCC undervoltage, the IC enters into the Auto Restart Mode and starts a new startup cycle. Short Optocoupler also leads to VCC undervoltage as there is no self supply after activating the internal reference and bias. In contrast to the Latched Off Mode, there is always a Startup Phase with switching cycles in Auto Restart Mode. After this Start Up Phase, the conditions are again checked whether the failure mode is still present. Normal operation is resumed once the failure mode is removed that had caused the Auto Restart Mode.
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Electrical Characteristics
4
Note:
Electrical Characteristics
All voltages are measured with respect to ground (Pin 8). The voltage levels are valid if other ratings are not violated.
4.1
Note:
Absolute Maximum Ratings
Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 7 (VCC) is discharged before assembling the application circuit.
Parameter Drain Source Voltage Pulse drain current, tp limited by Tjmax
Symbol VDS ICE3B0365L ID_Puls1 ICE3A1065L ID_Puls2 ICE3A1565L ID_Puls3 ICE3B0365L EAR1 ICE3A1065L EAR2 ICE3A1565L EAR3 ICE3B0365L IAR1 ICE3A1065L IAR2 ICE3A1565L IAR3 VVCC VFB VSoftS VCS Tj TS RthJA VESD -
Limit Values min. max. 650 1.6 3.4 6.1 0.005 0.07 0.15 0.3 1.0 1.5 22 6.5 6.5 6.5 150 150 90 3
Unit V A A A mJ mJ mJ A A A V V V V C C K/W kV
Remarks Tj=110C
Avalanche energy, repetitive tAR limited by max. Tj=150C1) Avalanche current, repetitive tAR limited by max. Tj=150C VCC Supply Voltage FB Voltage SoftS Voltage CS Voltage Junction Temperature Storage Temperature Thermal Resistance Junction -Ambient
-0.3 -0.3 -0.3 -0.3 -40 -55 -
PG-DIP-8-6 Human body model2)
ESD Capability(incl. Drain Pin)
1) 2)
Repetitive avalanche causes additional power losses that can be calculated as PAV=EAR*f According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5k series resistor)
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Electrical Characteristics 4.2
Note: Parameter VCC Supply Voltage Junction Temperature of Controller Junction Temperature of CoolMOSTM
Operating Range
Within the operating range the IC operates as described in the functional description. Symbol VVCC TjCon TjCoolMOS Limit Values min. VVCCoff -25 -25 max. 20 130 150 V C C Max value limited due to thermal shut down of controller Unit Remarks
4.3
4.3.1 Note:
Characteristics
Supply Section The electrical characteristics involve the spread of values within the specified supply voltage and junction temperature range TJ from - 25 C to 130 C. Typical values represent the median values, which are related to 25C. If not otherwise stated, a supply voltage of VCC = 15 V is assumed. Symbol min. IVCCstart IVCCcharge1 IVCCcharge2 IStartLeak IVCCsup_ng ICE3B0365L IVCCsup_g1 ICE3A1065L IVCCsup_g2 ICE3A1565L IVCCsup_g3 IVCClatch IVCCrestart 0.55 Limit Values typ. 160 1.05 0.88 0.2 5.5 5.5 5.9 6.3 300 300 max. 220 1.60 50 7.0 7.0 7.5 8.0 A mA mA A mA mA mA mA A A IFB = 0 ISofts = 0 IFB = 0 ISofts = 0 VVCC =15V VFB = 3.7V, VSoftS = 4.4V VVCC = 9.5V VFB = 3.7V, VSoftS = 4.4V VSoftS = 4.4V IFB = 0, VVCC =14V VVCC = 0V VVCC =14V VVCC=16V, VDrain = 450V at Tj=100C Unit Test Condition
Parameter Start Up Current VCC Charge Current Leakage Current of Start Up Cell and CoolMOSTM Supply Current with Inactive Gate Supply Current with Active Gate
Supply Current in Latched Off Mode Supply Current in Auto Restart Mode with Inactive Gate Supply Current in Active Burst Mode with Inactive Gate VCC Turn-On Threshold VCC Turn-Off Threshold VCC Turn-On/Off Hysteresis
IVCCburst1 IVCCburst2 VVCCon VVCCoff VVCChys
14.2 8.0 -
1.05 0.95 15.0 8.5 6.5
1.25 1.15 15.8 9.0 -
mA mA V V V
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Electrical Characteristics
4.3.2 Internal Voltage Reference Symbol min. Trimmed Reference Voltage VREF 6.37 Limit Values typ. 6.50 max. 6.63 V measured at pin FB IFB = 0 Unit Test Condition
Parameter
4.3.3 Parameter
PWM Section Symbol min. ICE3Axx65L fOSC_A1 fOSC_A2 92 94 61 63 0.67 0 3.5 0.3 16 39 Limit Values typ. 100 100 67 67 0.72 3.7 0.85 0.7 20 50 max. 108 106 73 71 0.77 3.9 4.75 27 62 V V V k k CS=1V, limited by Comparator C41) VFB < 0.3V kHz kHz kHz kHz Tj = 25C Tj = 25C Unit Test Condition
Fixed Oscillator Frequency
Fixed Oscillator Frequency
ICE3Bxx65L
fOSC_B1 fOSC_B2
Max. Duty Cycle Min. Duty Cycle PWM-OP Gain Voltage Ramp Max Level VFB Operating Range Min Level VFB Operating Range Max level FB Pull-Up Resistor SoftS Pull-Up Resistor
1)
Dmax Dmin AV VMax-Ramp VFBmin VFBmax RFB RSoftS
The parameter is not subjected to production test - verified by design/characterization
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Electrical Characteristics
4.3.4 Parameter Deactivation Level for SoftS Comparator C7 by C2 Clamped VSoftS Voltage during Normal Operating Mode Activation Limit of Comparator C3 SoftS Startup Current Over Load & Open Loop Detection Limit for Comparator C4 Active Burst Mode Level for Comparator C5 Active Burst Mode Level for Comparator C6a Active Burst Mode Level for Comparator C6b Overvoltage Detection Limit Latched Thermal Shutdown1) Spike Blanking Power Down Reset for Latched Mode
1)
Control Unit Symbol min. VSoftSC2 VSoftSclmp VSoftSC3 ISoftSstart VFBC4 VFBC5 VFBC6a VFBC6b VVCCOVP TjSD tSpike VVCCPD 3.85 4.23 5.20 4.62 1.23 3.85 3.25 20 130 4.0 Limit Values typ. 4.00 4.40 5.40 1.3 4.80 1.30 4.00 3.40 21 140 8.0 6.0 max. 4.15 4.57 5.60 4.98 1.37 4.15 3.55 22 150 7.5 V V V mA V V V V V C s V After Latched Off Mode is entered VFB > 5V VFB = 4V VFB > 5V VSoftS = 0V VSoftS > 5.6V VSoftS > 5.6V After Active Burst Mode is entered After Active Burst Mode is entered VFB > 5V Unit Test Condition
The parameter is not subjected to production test - verified by design/characterization The trend of all the voltage levels in the Control Unit is the same regarding the deviation except VVCCOVP and VVCCPD
Note:
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Electrical Characteristics
4.3.5 Parameter Peak Current Limitation (incl. Propagation Delay) Peak Current Limitation during Active Burst Mode Leading Edge Blanking CS Input Bias Current Over Current Detection for Latched Off Mode CS Spike Blanking for Comparator C11 Current Limiting Symbol min. Vcsth VCS2 tLEB ICSbias VCS1 tCSspike 0.97 0.232 -1.0 1.570 Limit Values typ. 1.02 0.257 220 -0.2 1.66 190 max. 1.07 0.282 0 1.764 V V ns A V ns VSoftS = 4.4V VCS =0V dVsense / dt = 0.6V/s (see Figure 12) Unit Test Condition
4.3.6
CoolMOSTM Section
Parameter Drain Source Breakdown Voltage Drain Source On-Resistance ICE3B0365L
Symbol min. V(BR)DSS RDSon1 600 650 -
Limit Values typ. 6.45 13.7 2.95 6.60 1.70 3.57 3.65 7.0 11.63 302) 302) max. 7.50 17.0 3.42 7.56 1.96 4.12 -
Unit V V pF pF pF ns ns
Test Condition Tj = 25C Tj = 110C Tj = 25C Tj=125C1) at ID = 0.3A Tj = 25C Tj=125C1) at ID = 1.0A Tj = 25C Tj=125C1) at ID = 1.5A VDS = 0V to 480V
ICE3A1065L
RDSon2
ICE3A1565L
RDSon3
Effective output capacitance, energy related Rise Time Fall Time
1) 2)
ICE3B0365L ICE3A1065L ICE3A1565L
Co(er)1 Co(er)2 Co(er)3 trise tfall
The parameter is not subjected to production test - verified by design/characterization Measured in a Typical Flyback Converter Application
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CoolSETTM-F3 ICE3xxx65L
Temperature derating curve
5
Temperature derating curve
Safe Operating Area for ICE3A(B)0365(L) ID = f ( VDS ) parameter : D = 0, TC = 25deg.C 10
1
ID [A]
0.1
0.01
tp = tp = tp = tp = tp = DC
0.01ms 0.1ms 1ms 10ms 100ms
0.001 1 10 V DS [V] 100 1000
Figure 20 Safe Operating area ( SOA ) curve for ICE3B03065L
Safe Operating Area for ICE3A(B)1065(L) ID = f ( VDS ) parameter : D = 0, TC = 25deg.C 10
1
ID [A]
0.1
0.01
tp = tp = tp = tp = tp = DC
0.1ms 1ms 10ms 100ms 1000ms
0.001 1 10 V DS [V] 100 1000
Figure 21 Safe Operating area ( SOA ) curve for ICE3A1065L
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Temperature derating curve
Safe Operating Area for ICE3A(B)1565(L) ID = f ( VDS ) parameter : D = 0, TC = 25deg.C 10
1
ID [A]
0.1
0.01
tp = tp = tp = tp = tp = DC
0.1ms 1ms 10ms 100ms 1000ms
0.001 1 10 V DS [V] 100 1000
Figure 22 Safe Operating area ( SOA ) curve for ICE3A1565L
SOA temperature derating coefficient curve for F3 & F2 CoolSET
120
SOA temperature derating coefficient [%]
100
80
60
40
20
0 0 20 40 60 80 100 120 140 Junction temperature Tc [deg.C]
Figure 23 SOA temperature derating coefficient curve
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CoolSETTM-F3 ICE3xxx65L
Outline Dimension
6
Outline Dimension
PG-DIP-8-6 (Plastic Dual In-Line Outline)
Figure 24 PG-DIP-8-6 ( Pb-free lead plating Platic Dual-in-Line Outline )
Dimensions in mm
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CoolSETTM-F3 ICE3xxx65L
Marking
7
Marking
Marking
Figure 25 Marking for ICE3B0365L Marking
Figure 26 Marking for ICE3A1065L
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CoolSETTM-F3 ICE3xxx65L
Marking Marking
Figure 27 Marking for ICE3A1565L
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CoolSETTM-F3 ICE3xxx65L
Schematic for recommended PCB layout
8
Schematic for recommended PCB layout
TR1
BR1 Spark Gap 3 FUSE1
R11 C11 bulk cap D11
C12
D21
L
Spark Gap 1
X-CAP C1 L1
Vo
C21
GND
Spark Gap 2 Spark Gap 4 C2 Y-CAP C3 Y-CAP C4 Y-CAP SOFTS/BL GND C13 R12 CS D11 Z11
GND
C16 R21
N
IC11
DRAIN R13 R14 D13
F3 CoolSET VCC
FB C15 NC
R23
R22 C22
*
C14
C23
R24
IC12
IC21 R25
F3 CoolSET schematic for recommended PCB layout
Figure 28 Schematic for recommended PCB layout
General guideline for PCB layout design using F3 CoolSET (refer to Figure 28): 1. "Star Ground "at bulk capacitor ground, C11: "Star Ground "means all primary DC grounds should be connected to the ground of bulk capacitor C11 separately in one point. It can reduce the switching noise going into the sensitive pins of the CoolSET device effectively. The primary DC grounds include the followings. a. DC ground of the primary auxiliary winding in power transformer, TR1, and ground of C16 and Z11. b. DC ground of the current sense resistor, R12 c. DC ground of the CoolSET device, GND pin of IC11; the signal grounds from C13, C14, C15 and collector of IC12 should be connected to the GND pin of IC11 and then "star "connect to the bulk capacitor ground. d. DC ground from bridge rectifier, BR1 e. DC ground from the bridging Y-capacitor, C4 2. High voltage traces clearance: High voltage traces should keep enough spacing to the nearby traces. Otherwise, arcing would incur. a. 400V traces (positive rail of bulk capacitor C11) to nearby trace: > 2.0mm b. 600V traces (drain voltage of CoolSET IC11) to nearby trace: > 2.5mm 3. Filter capacitor close to the controller ground: Filter capacitors, C13, C14 and C15 should be placed as close to the controller ground and the controller pin as possible so as to reduce the switching noise coupled into the controller. Guideline for PCB layout design when >3KV lightning surge test applied (refer to Figure 28): 1. Add spark gap Spark gap is a pair of saw-tooth like copper plate facing each other which can discharge the accumulated charge during surge test through the sharp point of the saw-tooth plate. a. Spark Gap 3 and Spark Gap 4, input common mode choke, L1: Gap separation is around 1.5mm (no safety concern)
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Schematic for recommended PCB layout
b. Spark Gap 1 and Spark Gap 2, Live / Neutral to GROUND: These 2 Spark Gaps can be used when the lightning surge requirement is >6KV. 230Vac input voltage application, the gap separation is around 5.5mm 115Vac input voltage application, the gap separation is around 3mm 2. Add Y-capacitor (C2 and C3) in the Live and Neutral to ground even though it is a 2-pin input 3. Add negative pulse clamping diode, D11 to the Current sense resistor, R12: The negative pulse clamping diode can reduce the negative pulse going into the CS pin of the CoolSET and reduce the abnormal behavior of the CoolSET. The diode can be a fast speed diode such as IN4148. The principle behind is to drain the high surge voltage from Live/Neutral to Ground without passing through the sensitive components such as the primary controller, IC11.
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Schematic for recommended PCB layout
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Total Quality Management
Qualitat hat fur uns eine umfassende Bedeutung. Wir wollen allen Ihren Anspruchen in der bestmoglichen Weise gerecht werden. Es geht uns also nicht nur um die Produktqualitat - unsere Anstrengungen gelten gleichermaen der Lieferqualitat und Logistik, dem Service und Support sowie allen sonstigen Beratungs- und Betreuungsleistungen. Dazu gehort eine bestimmte Geisteshaltung unserer Mitarbeiter. Total Quality im Denken und Handeln gegenuber Kollegen, Lieferanten und Ihnen, unserem Kunden. Unsere Leitlinie ist jede Aufgabe mit Null Fehlern" zu losen - in offener Sichtweise auch uber den eigenen Arbeitsplatz hinaus - und uns standig zu verbessern. Unternehmensweit orientieren wir uns dabei auch an top" (Time Optimized Processes), um Ihnen durch groere Schnelligkeit den entscheidenden Wettbewerbsvorsprung zu verschaffen. Geben Sie uns die Chance, hohe Leistung durch umfassende Qualitat zu beweisen. Wir werden Sie uberzeugen. Quality takes on an allencompassing significance at Semiconductor Group. For us it means living up to each and every one of your demands in the best possible way. So we are not only concerned with product quality. We direct our efforts equally at quality of supply and logistics, service and support, as well as all the other ways in which we advise and attend to you. Part of this is the very special attitude of our staff. Total Quality in thought and deed, towards co-workers, suppliers and you, our customer. Our guideline is "do everything with zero defects", in an open manner that is demonstrated beyond your immediate workplace, and to constantly improve. Throughout the corporation we also think in terms of Time Optimized Processes (top), greater speed on our part to give you that decisive competitive edge. Give us the chance to prove the best of performance through the best of quality - you will be convinced.
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